Aspects of the present disclosure relate generally to telecommunications, and more particularly, to self-powered clock input buffer.
Phase noise is the frequency domain representation of random fluctuations in the phase of a waveform. A phase-locked loop or a synthesizer in a modern wireless transceiver must meet stringent phase noise requirements in order to operate at high data rates. Although synthesizers may be designed for optimal phase noise performance, such performance is often limited by the noise on the reference input clock, which tends to be dominated by the loading of the Printed Circuit Board (PCB) reference input clock path. For example, an external regulator such as a Power Module Integrated Circuit (PMIC) provides power to the synthesizer block of most wireless transceivers. In addition, regulators also provide the reference input clock that the synthesizer uses to generate higher frequency clock signals. Yet, since the PMIC is external to the transceiver chip, it must drive the reference input clock across the PCB and through other device interconnects to reach the clock input buffer of the transceiver. Consequently, the signal integrity of the reference input clock (e.g., rise time, fall time, and jitter) at the input of the transceiver degrades, which causes an increase in the overall phase noise of the transceiver.
Conventional systems counter the effects of reference input clock noise on transceiver phase noise by powering the clock input buffer with a clean supply from a high quality regulator (e.g., good PSRR performance). However, these regulators generally consume more power, take up more space, and cost more.
Accordingly, there remains a need in the art for methods to improve the phase-noise performance of a synthesizer in a telecommunication circuit, without a trade-off on other critical performance parameters.